검색어: j'as (프랑스어 - 영어)

j' as trois frères.
i ...three brothers.

les moutonr. et chèvres n'ont j > as été comptabilisés dans ce total, leurs excreta ne se prêtant pas à la collecte.
sheep and goats have been excluded as their wastes are considered not amenable to collection.

unité centrale selon la revendication 1 caractérisée en ce que ledit dispositif d'interconnexion d'entrée (xe) est formé de plusieurs anneaux (as₁,...as j ,...as q ) de stations (stj i ) disposés en autant de niveaux, chaque anneau de station (as j ) étant identique audit anneau de station d'entrée (as₁), ledit anneau de stations d'entrée (as₁) constituant le premier niveau, ladite interface d'entrée parallèle étant alors formée par l'anneau de station (as 2 ) du second niveau, en ce que pour chaque mémoire (m i ) une interface d'entrée mémoire (iem i ) délivre un signal d'acquittement mémoire (ack i ), en ce que chaque station (stq i ) du dernier niveau a sa sortie reliée à l'interface d'entrée (iem i ) d'une mémoire associée (m i ) et reçoit sur son entrée d'acquittement (7) le signal d'acquittement mémoire (ack i-1 ) de l'interface d'entrée mémoire (iem i-1 ) qui est reliée à la station (stq (i-1) ) dudit dernier niveau et qui est située en amont de ladite station (stq i ), en ce que chaque station (stj i ) d'un autre niveau a sa sortie (3) reliée à la seconde entrée (4) d'une station (st(j+1) i ) appartenant au niveau directement supérieur et reçoit sur son entrée d'acquittement (7) le signal de notification (n(j+1) (i-1) ) issu de la station (st(j+1) (i-1) ) située en amont de ladite station appartenant audit niveau directement supérieur.
a central unit according to claim 1 characterised in that said input interconnection device (xe) is made up of several rings (as₁,...as i ,...as q ) of stations (stj i ) arranged in as many stages, each station ring (as j ) being identical to said input station ring (as₁), said input station ring (as₁) constituting the first stage, said parallel input interface then being formed by the station ring (as₂) of the second stage, in that for each memory (m i ) a memory input interface (iem i ) gives a memory acknowledgement signal (ack i ), in that each station (st qi ) of the last stage has its output connected to the input interface (iem i ) of an associated memory (m i ) and receives at its acknowledgement input (7) the memory acknowledgement signal (ack i-1 ) of the memory input interface (iem i ) which is connected to the station (stq (i-1) ) of said last stage and which is located upstream from said station (stqi), in that each station (stj i ) of another stage has its output (3) connected to the second input (4) of a station (st(j+1) i ) belonging to the stage directly above and receives at its acknowledgement input (7) the notification signal (n(j+1) (i-1) ) output from the station (st(j+1) (i-1) ) located upstream from said station belonging to said stage directly above.