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Η σύνθεση είναι η διδαδικασία της μεταγλώττισης της vhdl και η αντιστοίχισή της με μια τεχνολογία υλοποίησης όπως τα fpga ή τα asic.
synthesis is a process where a vhdl is compiled and mapped into an implementation technology such as an fpga or an asic.
* verilog* systemc* fpga* asic* janick bergeron, "writing testbenches: functional verification of hdl models", 2000, isbn 0-7923-7766-4.
* janick bergeron, "writing testbenches: functional verification of hdl models", 2000, isbn 0-7923-7766-4.