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התחביר כדלהלן: '*12'h123 - hexadecimal 123 (using 12 bits)*20'd44 - decimal 44 (using 20 bits - 0 extension is automatic)*4'b1010 - binary 1010 (using 4 bits)*6'o77 - octal 77 (using 6 bits)== ראו גם ==*vhdl* מדריך על ורילוג בעברית
the basic syntax is:'examples:*12'h123 - hexadecimal 123 (using 12 bits)*20'd44 - decimal 44 (using 20 bits - 0 extension is automatic)*4'b1010 - binary 1010 (using 4 bits)*6'o77 - octal 77 (using 6 bits)==synthesizeable constructs==there are several statements in verilog that have no analog in real hardware, e.g.
