전문 번역가, 번역 회사, 웹 페이지 및 자유롭게 사용할 수 있는 번역 저장소 등을 활용합니다.
Η σύνθεση είναι η διδαδικασία της μεταγλώττισης της vhdl και η αντιστοίχισή της με μια τεχνολογία υλοποίησης όπως τα fpga ή τα asic.
synthesis is a process where a vhdl is compiled and mapped into an implementation technology such as an fpga or an asic.
* verilog* systemc* fpga* asic* janick bergeron, "writing testbenches: functional verification of hdl models", 2000, isbn 0-7923-7766-4.
* janick bergeron, "writing testbenches: functional verification of hdl models", 2000, isbn 0-7923-7766-4.